Pseudo-random number generator, using cellular automata and a feed-back loop.
Xilinx XPS IP core of the Xillybus DMA interface, configured with 4 FIFOs (two host to FPGA, two FPGA to host)
Sound source localization utilizing 4, 8, or 16 PDM microphones and the Delay-Sum algorithm
General-purpose Instruction Computer Architecture is a 8-bit MCU/CPU RISC architecture
FPGA implementation of GZip compressor
Board support files for the V5IP7000 ASIC prototyping platform with the Virtex-5 LX330 FPGA. Designed for use with Xilinx ISE Platform Studio
Split-LUT-Carry (SLC) Self-Programmable Cellular Automaton (SPCA) Pseudo-Random Number Generator
FPGA implementation of the Baptista encryption algorithms
Utilitary circuits for AXI4 communication - register access over AXI4-Lite, data streaming with AXI Stream, DMA over AXI4-Burst, etc
Digital circuit which samples a pair of I2S microphones and transmits the samples to a PC, via UART, on request. Useful for sound recording, sound source localization, etc.