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Exemple pentru cursul de Programarea Calculatoarelor, anul 2018.

FPGA implementation of GZip compressor

Pynq integration of the Gzip FPGA compressor

A hybrid adaptive clock manager for Xilinx FPGAs. Adding to the functionality of the Mixed-Mode Clock Manager block, the HACM is capable of performing fine-grained frequency scaling.

Exemple de la cursul de Structuri de Date și Algoritmi - 2018

Utilitary circuits for AXI4 communication - register access over AXI4-Lite, data streaming with AXI Stream, DMA over AXI4-Burst, etc

Sound source localization utilizing 4, 8, or 16 PDM microphones and the Delay-Sum algorithm

Sound source localization utilizing 4, 8, or 16 PDM microphones and the Delay-Sum algorithm

Java app made to automate generation of support files required by Xilins XPS, in order to easily connect a user-defined core into a Xilinx system.

Xilinx XPS IP core of the Xillybus DMA interface, configured with 4 FIFOs (two host to FPGA, two FPGA to host)