Explore projects

Xilinx XPS IP core of the Xillybus DMA interface, configured with 4 FIFOs (two host to FPGA, two FPGA to host)

Pseudo-random number generator, using cellular automata and a feed-back loop.

Utilitary circuits for AXI4 communication - register access over AXI4-Lite, data streaming with AXI Stream, DMA over AXI4-Burst, etc

POO Tema 2 - Blur Filter

Exemplele date la cursul de POO de la seria F, în anul universitar 2017-2018.

Sound source localization utilizing 4, 8, or 16 PDM microphones and the Delay-Sum algorithm

Final project for RC

A board-level simulator with GUI for FPGA boards, based on Xilinx Vivado Simulator.

A Java tool to run quick multiple choices tests.